It is known to provide a data processing apparatus which is operable to support the processing of more than one instruction set. Supporting more than one instruction set may occur for various reasons. For example, one instruction set supported by the data processing apparatus may be optimised to be particularly speed efficient, whereas another instruction set supported by the data processing apparatus may be optimised to provide high code density.
In any event, when a data processing apparatus is required to support multiple instruction sets, for whatever reason, instructions from the different instruction sets need to be decoded for execution.
It is known to provide additional instruction decoders for each additional instruction set to be processed by the data processing apparatus. In this way, further instruction sets are included to be processed by the data processing apparatus, as required, and the further decoders are selected to enable those instruction sets to be correctly decoded so that correct control signals may be provided to the data processing apparatus to cause correct execution of the intended instruction.
Generally, when multiple instruction sets are provided, information other than the instruction itself would typically need to be provided to enable a determination be made regarding which instruction set the instruction belongs. This is because there may be at least some identical instruction encodings that decode to indicate different operations for different instruction sets. Accordingly, some other state information is typically required in order to determine which instruction set is currently selected and therefore which operation to perform.
Adding instructions sets is costly in terms of area, speed and power as, from a microprocessor architecture perspective, an entire additional decoder is added per instruction set.
It is desired to provide an improved technique for decoding instructions from a plurality of instruction sets.